I am an Electronics Engineer with High-Performance Computing and Hardware Acceleration expertise. I graduated as Electronics Engineer with honours from ITCR and as Master in High-Performance Computing from SISSA/ICTP in Italy. Currently, I am pursuing a second Master's in Electronics Engineering at ITCR, where I am researching about approximate Deep Learning inference acceleration on low-power devices, mainly on FPGAs.

I started programming in 2010, where I have been exposed to many fields, from Web, IOT, Electronics, and Linux. I have three years of experience in Industry, working for RidgeRun LLC and eXact Lab. I am also a postgraduate researcher at ITCR, where I collaborate with Approximate Computing topics.

Advanced C/C++   Linux Kernel   Internet of Things   Approximate Computing   High-Level Synthesis   Parallel Computing   Distributed Computing   MPI/OpenMP/CUDA/OpenACC stack   HPC (Torque, Slurm)   Hardware Acceleration   NodeJS   Technical Architecture   Backend Machine learning   GStreamer  

My theses

• Lic: Designing an Embedded Traffic Dynamics Meter: A case study. Download
• MHPC: NanoSciTracker: an object tracking library for microbiology and an industrial collimation algorithm optimisation. Download
• M.Sc (In progress): Design of a library of parameterised accelerators of DNN-based inference algorithms at the Edge with FPGAs and Approximate Computing

Supervised work

• Thesis: Randall Bonilla [I-2019/Finished]: Design of a software application for the automatic computing a PID controller of DC/DC Converters
• Thesis: Daniel Castro [I-2021/Finished/Cum laude]: Redesign and integration of the control/power PCBs in an EV charger
• Thesis: Cristhian Rojas [I-2021/Finished]: Design of an unified platform based on microservices for managing the EV chargers
• Thesis: David Picado [I-2021/Finished]: Design of an OCPP-compliant firmware for EV chargers
• Thesis: Alejandro Rodriguez [II-2021/On-going]: Design of a hardware accelerator for computing fast CNN convolutions on FPGAs
• Thesis: Eduardo Salazar [II-2021/Finished/Cum laude]: Design of a configurable processing element to accelerate deep neural networks
• Thesis: Edgar Chaves [II-2021/Finished]: Implementing of a hardware accelerated Smart Parking application with GStreamer and TensorFlowLite on an i.MX8M Plus
• Design Project: Jose Ortega [II-2021/Finished]: Design of a microkernel-based open cloud service provider
• Design Project: Fabricio Elizondo [I-2022/On-going]: Design and implementation of approximate activation functions for DCNNs
• Design Project: David Cordero [I-2022/On-going]: Design and implementation of a testbench for testing approximations on DNNs using TensorFlow
• Thesis: Erick Obregon [I-2022/On-going]: Design and implementation of TFLite Delegate for the Flexible Accelerators Library (FAL) on FPGAs
• Thesis: Esteban Campos [I-2022/On-going]: Design and implementation of Linux Device Drivers for the Flexible Accelerators Library (FAL) on FPGAs
• Thesis: Jose Ortega [I-2022/On-going]: Design and Implementation of a microkernel-based open cloud service provider

Publications

• Luis G. León-Vega, Jorge Castro-Godínez, Jörg Henkel. Measuring Traffic Dynamics at the Edge, in International Work Conference on Bioinspired Intelligence (IWOBI), UCR & TEC, Costa Rica, October 21-23, 2020.
• Luis G. León-Vega, Kaleb Alfaro-Badilla, Alfonso Chacón-Rodríguez, Carlos Salazar-García. Optimizing Big Data Network Transfers in FPGA SoC Clusters: TECBrain Case Study, in Latin American High Performance Computing Conference (CARLA 2019), Costa Rica, September 25-27, 2019.
• Kaleb Alfaro-Badilla, Andrés Arroyo-Romero, Carlos Salazar-García, Luis G. León-Vega, Javier Espinoza-González, Franklin Hernández-Castro, Alfonso Chacón-Rodríguez, Georgios Smaragdos, Christos Strydis. Improving the Simulation of Biologically Accurate Neural Networks Using Data Flow HLS Transformations on Heterogeneous SoC-FPGA Platforms , in Latin American High Performance Computing Conference (CARLA 2019), Costa Rica, September 25-27, 2019.
• Luis G. Leon-Vega, Eduardo Salazar-Villalobos, Jorge Castro-Godínez. Accelerating Machine Learning at the Edge with Approximate Computing on FPGAs, in Bioinspired Processing 2021 Special Issue(BIP), Costa Rica, November 4th, 5th 2021. (Approved)
• Jose Ortega Gonzalez, Luis G. Leon-Vega. Design of a Microkernel-based Cloud Manager for IoT Services, in Bioinspired Processing 2021 Special Issue(BIP), Costa Rica, November 4th, 5th 2021. (Approved)
• Edgar Chaves Gonzalez, Luis G. Leon-Vega. Benchmarking the NXP i.MX8M+ Neural Processing Unit, in Bioinspired Processing 2021 Special Issue(BIP), Costa Rica, November 4th, 5th 2021. (Approved)

High-Performance Computing: In the last 2 years, I have been working in algorithm optimisation for soft/firm real-time applications in multimedia streaming and industrial applications. I am currently specialist in intrinsics (AVX2/AVX512/NEON), multi-threading (OpenMP), distributed computing (OpenMPI/IntelMPI), and general-purpose graphics acceleration (CUDA). Additionally, it has involved deep knowledge about system's architecture and FORTRAN/C/C++ languages at compiler level to unlock the potential of software implementations. I have written the following article for RidgeRun's blog

Hardware Acceleration: My research field of interest is hardware acceleration on low-power devices like FPGAs. I am currently specialised in High-Level Synthesis on Xilinx platforms. I am currently working on the deep learning inference acceleration at the Edge, where I am supervising a couple of bachelor's theses related to IP Core generation for fast Matrix-Matrix multiplication and Winograd/FFT Convolution.

Linux: As part of my duties, I am familiarised with the Linux kernel and its internal structures, specially, for creating device drivers for camera sensors, and I2C devices. Most software I work on run on Linux.

Internet of Things: I am currently working on a software backbone for supporting serverless IoT applications based on function lambdas (similar to AWS) with MQTT and multi-database support. The idea is to offer an open source solution for baremetal deployments